The invention relates to a semiconductor structure and processing method, and more particularly to an improved structure and method for a metal gate structure of a high performance device.
In the semiconductor fabrication industry, transistors have typically been formed utilizing polysilicon gate electrodes. Polysilicon has been preferred because of its thermal robustness and other special characteristics. An important feature of polysilicon gates is that they can withstand the processing of other elements of transistors such as source and drain regions, during dopant drive-in or other high temperature processes such as annealing processes.
However, as used in transistors, polysilicon gates are less advantages than metal gates. A polysilicon gate is subject to the formation of a depletion region in operation in which charge carriers are depleted from the polysilicon material above the gate dielectric. This varies from a metal electrode in which charge carriers remain plentiful throughout the electrode. The depletion region has the effect of making the gate dielectric appear thicker in operation than it actually is, such that more charge is needed to turn on the transistor having the polysilicon gate than the transistor having the metal gate. Another disadvantage of polysilicon gates is its incompatibility with high-k dielectric materials. Moreover, polysilicon, even when highly doped to dopant concentrations up to 1020cm −3, is not nearly as good a conductor as metal. This causes polysilicon gates to operate at a slower speed than metal gates. For these reasons, as design requirements demand better performance, metal gates are favored.
The alternative to using polysilicon gates is fabrication and use of metal gates instead. Metals are much better conductors of electricity, resulting in reduced gate contact resistance, which provides faster device performance. Manufacturing of metal gates, however, can pose serious challenges. For one, metal gates are not thermally robust like polysilicon and therefore cannot be exposed to high temperatures during processing of transistors or other elements of integrated circuits (ICs). Furthermore, metal gates cannot withstand the oxidation ambient necessary to form polysilicon transistor gates. In addition, patterning accuracy required in gate formation is reduced when performing photolithography or other similar techniques on metal surfaces. The reason for this is that photolithography is better achieved on planar surfaces not easily obtainable in metals.
In recent years, there has been an effort to overcome the limitations of metal gate processing and the operational deficiencies of polysilicon gates through a process of forming transistor structures initially having polysilicon gates which are better able to withstand the initially more severe processing conditions. Thereafter, in later stages of processing when processing conditions are less severe, the polysilicon gates are removed from the structures and replaced with metal gates. By this replacement gate process, the initial severe process conditions need not be modified, and the photolithography benefits associated with polysilicon processing are preserved. The initial use of polysilicon gates also takes advantage of the ability of polysilicon to block ion-implantation to the channel region of the transistor when performing source and drain implants to the transistor.
In a replacement gate fabrication approach, a polysilicon gate is formed over an etch stop layer in contact with a single-crystal semiconductor region of a substrate, a pair of spacers being disposed on sidewalls of the gate. The etch stop layer is typically a thin layer of silicon dioxide which is grown thermally on the surface of the substrate in an oxygen ambient. In such case, the etch stop layer can be referred to as a sacrificial gate oxide layer. Later, the polysilicon material is removed from between the pair of spacers, as by an anisotropic vertical etch process such as a reactive ion etch (RIE) stopping on the etch stop layer. The etch stop layer is then cleared from the surface of the substrate as by a dry etch or an isotropic wet etch selective to the material of the sidewall spacers. This creates an opening between the spacers where a gate dielectric, usually a thermally grown oxide, is then formed. Thereafter, a metal gate is formed in the opening between the spacers contacting the gate dielectric underneath.
A preferred metal for forming such metal gates is tungsten (W). Tungsten is usually deposited using a chemical vapor deposition step (CVD) where a deposition precursor including a (source) gas such as WF6 is used. A particular challenge arises in the deposition of tungsten, however, especially when using WF6 as the deposition precursor. Fluorine radicals in the WF6 gas can be harmful both to oxide and silicon substances. Consequently, the fluorine gas can attack gate oxide and the silicon below the gate oxide. A different gas such as W(CO)6 may alternatively be used but the non-conformal properties of W(CO)6 can cause the formation of a defective tungsten gate. FIG. 1 illustrates the non-conformal tungsten properties of deposition using a W(CO)6 gas, leading to the pinch-off of the opening and a defective tungsten gate formation.
In FIG. 1, W(CO)6 110 has been deposited to coat the gate opening 100. The spacers are shown at 105. As illustrated in 115, the non-conformal characteristics of W(CO)6, especially when deposited in thick layers of 10 nm or more, create a pinchoff at the top of the gate opening 100 is filled. In addition, the non-conformal property of such deposition causes tungsten to accumulate unevenly so that a void is created in the middle or center of the tungsten gate, rendering the gate structurally defective. The pinchoff problem is extremely challenging in high performance environments where the width of the opening is narrow.
Another challenge, when using either WF6 or W(CO)6 gases, is that effective deposition of tungsten requires a good nucleation site to be present on the surfaces (i.e. sidewalls) where it is being deposited. The presence of oxides, especially on surfaces, affect the ability of tungsten to be deposited and to adhere properly to the surfaces it is being deposited on. Ineffective deposition of tungsten can lead to structurally defective gates in which the gate conductor material may peel or pop off from their adjacent surfaces.
An improved method is therefore required that enables the formation of metal gates, particularly those including tungsten as the predominant metal that addresses the processing challenges faced in the above-described processing methods.